South Korean memory chipmaker SK hynix Inc. officially unveiled its next-generation DRAM technology roadmap on Tuesday, including the 4F square (4F²) vertical gate (VG) platform and 3D DRAM, at the IEEE VLSI Symposium 2025, a prestigious academic conference in semiconductor circuit and process technology.

Cha Seon-yong, chief technology officer (CTO) and head of SK Hynix’s DRAM Development, presented the roadmap during a keynote speech at the event.

The IEEE VLSI Symposium is one of the world’s most authoritative academic forums where cutting-edge research on next-generation semiconductors, AI chips, memory, and packaging is presented. It is held alternately in the United States and Japan each year, with the 2025 edition taking place in Kyoto, Japan through June 12th, 2025.

“Current tech platforms applied to ultra-fine processes are reaching limits in performance and capacity,” Cha noted. “To overcome this, we are working on the 4F² VG platform and 3D DRAM based on innovations in architecture, materials, and components at sub-10 nanometer (nm) nodes to break through technical boundaries.”

The 4F² VG platform is a next-generation memory technology that minimizes DRAM cell area and enables high density, high speed, and low power consumption through a vertical gate structure. DRAM stores data in individual cells, and the area occupied by a single cell is typically expressed as F², where F is the minimum feature size of a semiconductor process.

A 4F² cell thus occupies an area of 2F by 2F, allowing more cells to be integrated into a single chip. The VG structure refers to a design where the gate, which acts as a transistor switch in DRAM, is erected vertically, surrounded by the channel.

6F² cells are currently standard but combining 4F² cells with wafer bonding technology - which places circuit components below the cell area - can significantly improve both cell efficiency and electrical characteristics, SK hynix explained.

Cha also highlighted 3D DRAM as a core pillar of the company’s future DRAM technology.

While some in the industry expect manufacturing costs for 3D DRAM to rise with the number of stacked layers, SK hynix aims to overcome this through technological innovation and secure a competitive edge. The company also plans to advance core materials and DRAM component technologies, establishing a foundation to sustain DRAM technology evolution for the next 30 years.

“Around 2010, many believed 20nm would be the limit for DRAM but continued innovation has brought us to where we are today,” Cha said. “We aim to present a long-term innovation vision that will serve as a milestone for young engineers entering DRAM development and work together with the industry to turn the future of DRAM into reality.”

SK hynix Vice President Park Joo-dong, who leads the next-generation DRAM task force, will present the latest research results validating the electrical characteristics of DRAM using VG and wafer bonding technologies on the final day of the event, June 12th.

[ⓒ 매일경제 & mk.co.kr, 무단 전재, 재배포 및 AI학습 이용 금지]